DVCon US
Design & verification (EDA functional verification) conference (Accellera/DVCon)
About this event
The 39th annual DVCon US, held at the Hyatt Regency Santa Clara and sponsored by Accellera Systems Initiative. The industry's most comprehensive technical programme on electronic system and IC design and verification, covering systems, ASIC, DSP, microprocessor, FPGA, analog/mixed-signal and SoC design disciplines including coverage-driven verification, low-power design, formal methods and machine learning applications.
Who it's for
Genuinely useful for hardware verification and design-automation professionals working on RTL/SoC design, formal verification, EDA tooling, and functional safety in silicon. Not relevant to AEC/BIM/construction-tech audiences, this is a pure semiconductor/EDA event with no crossover into digital engineering for the built environment.
Social media & coverage
“The post invites attendees to DVCon US 2025, the Design & Verification Conference & Exhibition, February 24-27, 2025 in San Jose, CA.”
“The post invites attendees to DVCon U.S., the Design & Verification Conference & Exhibition, February 24-27, 2025 in San Jose, CA.”
“SmartDV was on the DVCon U.S. show floor discussing Design IP and Verification IP and flexible IP adoption.”
Official hashtags
Used by the organiser on X and LinkedIn. Follow along before, during and after the event.